Charge transfer devices such as CCDs have gained popularity in recent years for performing a wide variety of electronic functions including signal processing, signal delay and image sensing.
Charge transfer devices typically include a CCD line register which transfers charge packets to a charge sensing stage. In a CCD imager, for example, an array of charge collecting regions formed in a semiconductor substrate collects image-representative charge packets in response to an incident radiation image. These charge packets are periodically transferred to the CCD line register. The charge sensing stage includes a periodically reset floating element for developing a voltage signal having amplitude variations responsive to the serially supplied image-representative charge packets. Typically, an on-chip FET amplifier, sometimes called an "electrometer", connected to the floating element provides the imager output signal. The FET amplifier contributes two noise components to the imager output signal. The first component, commonly called "1/f" noise, is predominant at lower video-frequencies of the imager output signal, and the second component is substantially uniformly distributed over the video frequency range and establishes a minimum noise level at the higher video-frequencies. The process of periodically resetting the floating element contributes a third noise component to the imager output signal, commonly called "reset noise". Reset noise results from variations in potential left upon the floating element from one reset interval to the next. Its magnitude is proportional to the square root of the capacitance of the floating element. At the upper video-frequencies of the imager output signal, the reset noise component maybe 10-15 db larger than the minimum noise level established by the FET amplifier.
The desirability of reducing both 1/f noise and reset noise has led to the practice of correlated double sampling signal recovery. In this technique the signal on the floating element is sampled twice. First, at a time when charge dependent on reset noise, but not signal, is present in the potential well induced "under" the floating element and, second, at a time when charge dependent on reset noise and signal is present in the potential well. Each sample pair is differentially combined so as to substantially reduce the reset noise and thereby generate samples which depend substantially only on the signal. The FET amplifier induced 1/f noise is also substantially reduced by the differential combining process since it is slowly varying and has substantially the same magnitude during the first and second sample time periods. Correlated double sampling becomes less practical as its sampling rates increase. The width and spacing of the sampling pulses are reduced towards the limits imposed by the time required for charge settling under the floating element. As clock rates rise to more than a few megahertz, the correlated double sampling technique becomes progressively more difficult to employ.
U.S. Pat. No. 4,330,753 issued May 18, 1982 to L. N. Davy and entitled METHOD AND APPARATUS FOR RECOVERING A SIGNAL FROM A CHARGE TRANSFER DEVICE, describes a relatively low noise method for signal recovery from a charge transfer device output stage which includes a periodically reset FET coupled to a floating element. The FET output signal is passed through a bandpass filter (BPF) to separate the double-sideband amplitude-modulated (DSB-AM) component centered about the sixth multiple of the clocking frequency. This DSB-AM signal is heterodyned, using a synchronous detector type of demodulator, to provide a baseband spectrum signal as the recovered signal from the charge transfer device. The Davy method is effective for suppressing the 1/f noise component for two reasons. Firstly, the 1/f noise is principally confined to the lower frequency spectrum of the device output, which is suppressed by the BPF. Secondly, the 1/f noise component is at a relatively insignificant signal level as compared to the information signal level, at the multiple of the DSB-AM signal frequency which is heterodyned. Additionally, the relative duty factors and timing of the device clock signals and the device output signal are adjusted so that the amplitude of the clock signal components appearing about the sixth harmonic of the output signal are zero (theoretically). Although this reduces feedthrough of clock signals to the output signal, the reduction of reset noise (which is unrelated to clock feedthrough) is not specifically addressed by Davy. Furthermore, the information signal component of the output signal centered about the sixth multiple of the clocking frequency is relatively small and therefore the output signal may have a poor signal-to-noise characteristic. Additionally, a very wideband on-chip FET amplifier is necessary so as to pass the sixth multiple component of the output signal.